I enjoyed reading a recent Bloomberg article, “How Intel Makes a Chip“. The comparison of processors versus airliners was eye opening, and I loved some of the jargon used within Intel.

Some interesting excerpts:

• Over the next three months—three times the amount of time it takes Boeing to manufacture a single Dreamliner—these wafers will be transformed into microprocessors.

• Simply building a fab capable of producing a chip like the E5 costs at least $8.5 billion, according to Gartner, and that doesn’t include the costs of research and development ($2 billion-plus) or of designing the circuit layout (more than $300 million). Even modest “excursions”—Intel’s euphemism for screw-ups—can add hundreds of millions of dollars in expense. The whole process can take five years or more.

• …paper, which sheds microscopic particles, is absolutely banned. If you want to write on something, you’ll have to use what is known in the industry as “high-performance documentation material,” a paperlike product that doesn’t release fibers.

• Every three years or so, Intel shrinks the dimensions of its transistors by about 30 percent. It went from 32-nanometer production in 2009 to 22nm in 2011 to 14nm in late 2014, the state of the art. Each

• The cleanroom is nearly silent except for the low hum of the “tools,” as Intel calls them, which look like giant copy machines and cost as much as $50 million each. They sit on steel pedestals that are attached to the building’s frame, so that no vibrations—from other tools, for instance, or from your footfalls—will affect the chips. You step softly even so. Some of these tools are so precise they can be controlled to within half a nanometer, the width of two silicon atoms.

• The company recently announced layoffs of 11 percent of its workforce, as CEO Brian Krzanich puts it, to “reinvent ourselves.”

• “These are thinner and straighter,” he says proudly, gesturing at a recent photograph, taken with an electron microscope, that shows two stock-straight black shadows resting eerily on a grayish base. The images look like dental X-rays. Intel people call them “baby pictures.”

• Madison!

  The man in charge of the Xeon E5’s wiring is Kevin Fischer, a midlevel Intel engineer who sat down in his Oregon lab in early 2009 with a simple goal: Fix the conductivity of two of the most densely packed layers of wires, known as Metal 4 and Metal 6. Fischer, 45, who has a Ph.D. in electrical engineering from the University of Wisconsin at Madison.

• Customer specific circuitry!

  There are other special circuits on the E5, but Intel can’t talk about those because they’re created for its largest customers, the so-called Super 7: Google, Amazon, Facebook, Microsoft, Baidu, Alibaba, and Tencent. Those companies buy—and often assemble for themselves—Xeon-powered servers by the hundreds of thousands. If you buy an off-the-shelf Xeon server from Dell or HP, the Xeon inside will contain technology that’s off-limits to you. “We’ll integrate [a cloud customer’s] unique feature into the product, as long as it doesn’t make the die so much bigger that it becomes a cost burden for everyone else,” says Bryant. “When we ship it to Customer A, he’ll see it. Customer B has no idea that feature is there.”

• I never considered this before, but it’s pretty crazy to think about!

  The individual transistors themselves are smaller than any wave of light. “When you get dimensions that small, color has no meaning,” he says, and then excuses himself.